CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 327

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.19.16
Datasheet
PLMLIMIT_REG - Protected Low-Memory Limit Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to setup the limit address of DMA protected low-memory region below 4 GB.
This register must be setup before enabling protected memory through PMEN_REG,
and must not be updated when protected memory regions are enabled.
This register is always treated as RO for implementations not supporting protected low
memory region (PLMR field reported as 0 in the Capability register).
The alignment of the protected low memory region limit depends on the number of
reserved bits (N) of this register. Software may determine the value of N by writing all
1's to this register, and finding most significant zero bit position with 0 in the value read
back from the register. Bits N:0 of the limit register is decoded by hardware as all 1s.
The Protected low-memory base & limit registers functions as follows.
Software must not modify this register when protected memory regions are enabled.
(PRS field Set in PMEN_REG).
•
•
31:21
20:0
Bit
Programming the protected low-memory base and limit registers with the same
value in bits 31:(N+1) specifies a protected low-memory region of size 2^(N+1)
bytes.
Programming the protected low-memory limit register with a value less than the
protected low-memory base register disables the protected low-memory region.
Access
RW
RO
000000h
Default
Value
000h
Protected Low-Memory Limit (PLML)
This register specifies the last host physical address of the
DMA protected low-memory region in system memory.
Reserved
0/0/0/DMIVC1REMAP
6C-6Fh
00000000h
RO; RW
32 bits
Description
327