CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 158

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.13.8
1.13.9
158
HDR1 - Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register identifies the header layout of the configuration space. No physical
register exists at this location.
PBUSN1 - Primary Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register identifies that this “virtual” Host-PCI Express bridge is connected to PCI
Bus 0.
7:0
7:0
Bit
Bit
Access
Access
RO
RO
Default
Value
Default
Value
01h
00h
Header Type Register (HDR)
Returns 01 to indicate that this is a single function device with
bridge header layout.
Primary Bus Number (BUSN)
Configuration software typically programs this field with the
number of the bus on the primary side of the bridge. Since
Device 1 is an internal device and its primary bus is always
0, these bits are read only and are hard wired to 0.
0/1/0/PCI
Eh
01h
RO
8 bits
0/1/0/PCI
18h
00h
RO
8 bits
Processor Configuration Registers
Description
Description
Datasheet