CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 385

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
125:124
123:104
103:96
95:80
79:64
63:36
35:12
11:0
Bit
Access
RO-P
RO-P
RO-P
RO
RO
RO
RO
RO
0000000h Output Enable for TXPlus-side Transmit Buffer
000000h
Default
00000h
Value
0000h
0000h
000h
00h
00b
Address Type (AT)
This field captures the AT field from the faulted DMA
request.
Hardware implementations not supporting Device-IOTLBs
(DI field Clear in Extended Capability register) treat this
field as RsvdZ.
When supported, this field is valid only when the F field is
Set, and when the fault reason (FR) indicates one of the
DMA-remapping fault conditions.
Reserved
Fault Reason (FR)
Reason for the fault. Appendix A enumerates the various
translation fault reason encodings.
This field is relevant only when the F field is Set.
Reserved
Source Identifier (SID)
Requester-id associated with the fault condition. This field
is relevant only when the F field is Set.
(TXPOE)
If TOE is set, this bit controls the TXPOEB enable directly,
otherwise if this bit is cleared it this bit directs the state
machine to keep this bit cleared. Enables P-side of final TX
driver.
0 = Enable
1 = Disable
Page Address (PADDR)
When the Fault Reason (FR) field indicates one of the DMA-
remapping fault conditions, Bits 63:12 of this field contains
the page address in the faulted DMA request. Hardware
treat Bits 63:N as reserved (0), where N is the maximum
guest address width (MGAW) supported.
When the Fault Reason (FR) field indicates one of the
interrupt-remapping fault conditions, Bits 63:48 of this field
indicate the interrupt_index computed for the faulted
interrupt request, and Bits 47:12 are cleared.
This field is relevant only when the F field is Set.
Reserved
(Sheet 2 of 2)
Description
385