CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 166

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.13.21
166
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40- bit address. The lower 8 bits of the Upper Limit Address register
are read/write and correspond to address bits A[39:32] of the 40-bit address. This
register must be initialized by the configuration software. For the purpose of address
decode address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range is at the top of a 1-MB aligned memory block.
Note that prefetchable memory range is supported to allow segregation by the
configuration software between the memory ranges that must be defined as UC and the
ones that can be designated as a USWC (i.e., prefetchable) from the CPU perspective.
CAPPTR1 - Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The capabilities pointer provides the address offset to the location of the first entry in
this device's linked list of capabilities.
31:0
7:0
Bit
Bit
Access
Access
RW
RO
00000000h Prefetchable Memory Address Limit (MLIMITU)
Default
Default
Value
Value
]8 bits
88h
First Capability (CAPPTR1)
The first capability in the list is the Subsystem ID and
Subsystem Vendor ID Capability.
Corresponds to A[63:32] of the upper limit of the
prefetchable Memory range that is passed to PCI Express-G.
0/1/0/PCI
34h
88h
RO
Processor Configuration Registers
Description
Description
Datasheet