CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 110

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.9.32
110
C1ODTCTRL - Channel 1 ODT Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
ODT controls.
31:12
11:8
7:4
3:0
Bit
Access
RW
RW
RW
RO
Default
00000h
Value
0h
0h
0h
Reserved
DRAM ODT for Read Commands
Specifies the duration to assert DRAM ODT for Read
Commands. The Async value should be used when the
Dynamic Powerdown bit is set. Else use the Sync value.
DRAM ODT for Write Commands
Specifies the duration to assert DRAM ODT for Write
Commands. The Async value should be used when the
Dynamic Powerdown bit is set. Else use the Sync value.
MCH ODT for Read Commands
Specifies the duration to assert MCH ODT for Read
Commands.
0/0/0/MCHBAR
69C-69Fh
00000000h
RO; RW
32 bits
Processor Configuration Registers
Description
Datasheet