CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 171

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.13.26
Datasheet
PM_CS1 - Power Management Control/Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:16
14:13
12:9
7:4
Bit
15
8
3
2
Access
RW-S
RO
RO
RO
RO
RO
RO
RO
Default
Value
0000h
0000b
00b
0b
0h
0b
1b
0b
Reserved
Not Applicable or Implemented. Hard wired to 0.
PME Status (PMESTS)
Indicates that this device does not support PMEB generation
from D3cold.
Data Scale (DSCALE)
Indicates that this device does not support the power
management data register.
Data Select (DSEL)
Indicates that this device does not support the power
management data register.
PME Enable (PMEE)
Indicates that this device does not generate PMEB assertion
from any D-state.0:PMEB generation not possible from any D
State
1 = PMEB generation enabled from any D State
The setting of this bit has no effect on hardware.See
PM_CAP[15:11]
Reserved
No Soft Reset (NSR)
When set to 1 this bit indicates that the device is transitioning
from D3hot to D0 because the power state commands do not
perform an internal reset. Config context is preserved. Upon
transition no additional operating sys intervention is required
to preserve configuration context beyond writing the power
state bits.
When clear the devices do not perform an internal reset upon
transitioning from D3hot to D0 via software control of the
power state bits.
Regardless of this bit, the devices that transition from a D3hot
to D0 by a system or bus segment reset will return to the
device state D0 un-initialized with only PME context preserved
if PME is supported and enabled.
Reserved
0/1/0/PCI
84-87h
00000008h
RO; RW-S; RW
32 bits
(Sheet 1 of 2)
Description
171