CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 303

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
53:48
47:40
37:34
33:24
Bit
39
38
Access
RO
RO
RO
RO
RO
RO
Default
Value
020h
09h
00h
1b
0b
0h
Maximum Address Mask Value (MAMV)
The value in this field indicates the maximum supported
value for the Address Mask (AM) field in the Invalidation
Address (IVA_REG) register.
This field is valid only when the PSI field is reported as Set.
Number of Fault-recording Registers (NFR)
This field indicates a value of N-1, where N is the number of
fault recording registers supported by hardware.
Implementations must support at least one fault recording
register (NFR = 0) for each DMA remapping hardware unit in
the platform.
The maximum number of fault recording registers per DMA-
remapping hardware unit is 256.
Page Selective Invalidation Support (PSI)
0 = Hardware supports only domain and global invalidates
1 = Hardware supports page selective, domain, and global
Reserved
Super Page Support (SPS)
This field indicates the super page sizes supported by
hardware.
A value of 1 in any of these bits indicates the corresponding
super-page size is supported. The super-page sizes
corresponding to various bit positions within this field are:
0: 21-bit offset to page frame
1: 30-bit offset to page frame
2: 39-bit offset to page frame
3: 48-bit offset to page frame
Hardware implementations supporting a specific super-page
size must support all smaller super-page sizes. i.e., the only
valid values for this field are 0001b, 0011b, 0111b, 1111b.
Fault-recording Register Offset (FRO)
This field specifies the location to the first fault recording
register relative to the register base address of this DMA-
remapping hardware unit. If the register base address is X,
and the value reported in this field is Y, the address for the
first fault recording register is calculated as X+(16*Y).
for IOTLB.
invalidates for IOTLB and hardware must support a
minimum MAMV value of 9.
(Sheet 2 of 5)
Description
303