CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 204

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.14.3
1.14.4
204
PVCCAP2 - Port VC Capability Register 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Describes the configuration of PCI Express Virtual Channels associated with this port.
PVCCTL - Port VC Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:24
23:8
15:4
7:0
3:1
Bit
Bit
0
Access
Access
RW
RO
RO
RO
RO
RO
Default
Default
0000h
Value
Value
000h
000b
00h
00h
0b
VC Arbitration Table Offset (VCATO)
field contains the zero-based offset of the table in
DQWORDS (16 bytes) from the base address of the
Virtual Channel Capability Structure. A value of 0
indicates that the table is not present (due to fixed VC
priority).
Reserved
Reserved for VC Arbitration Capability (VCAC)
Reserved
VC Arbitration Select (VCAS)
This field is programmed by software to the only possible
value as indicated in the VC Arbitration Capability field.
Since there is no other VC supported than the default,
this field is reserved.
Reserved for Load VC Arbitration Table
Used for software to update the VC Arbitration Table when
VC arbitration uses the VC Arbitration Table. As a VC
Arbitration Table is never used by this component this
field will never be used.
0/1/0/MMR
108-10Bh
00000000h
32 bits
0/1/0/MMR
10C-10Dh
0000h
16 bits
Indicates the location of the VC Arbitration Table. This
RO
RO; RW
Processor Configuration Registers
Description
Description
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