CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 206

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.14.6
206
VC0RCTL - VC0 Resource Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Controls the resources associated with PCI Express Virtual Channel 0.
30:27
26:24
23:20
19:17
15:8
7:1
Bit
31
16
0
Access
RW
RW
RO
RO
RO
RO
RO
RO
RO
Default
Value
000b
000b
00h
7Fh
1b
0h
0h
0b
1b
VC0 Enable (VC0E)
For VC0 this is hard wired to 1 and read only as VC0 can
never be disabled.
Reserved
VC0 ID (VC0ID)
Assigns a VC ID to the VC resource. For VC0 this is hard
wired to 0 and read only.
Reserved
Port Arbitration Select (PAS)
Port Arbitration Select – This field configures the VC
resource to provide a particular Port Arbitration service.
This field is valid for RCRBs, Root Ports that support peer
to peer traffic, and Switch Ports, but not for PCI Express
Endpoint devices or Root Ports that do not support peer to
peer traffic. The permissible value of this field is a number
corresponding to one of the asserted bits in the Port
Arbitration Capability field of the VC resource.
Reserved
Reserved for Load Port Arbitration Table ()
Reserved
TC/VC0 Map (TCVC0M)
Indicates the TCs (Traffic Classes) that are mapped to the
VC resource. Bit locations within this field correspond to
TC values. For example, when bit 7 is set in this field, TC7
is mapped to this VC resource. When more than one bit in
this field is set, it indicates that multiple TCs are mapped
to the VC resource. In order to remove one or more TCs
from the TC/VC Map of an enabled VC, software must
ensure that no new or outstanding transactions with the
TC labels are targeted at the given Link.
TC0/VC0 Map (TC0VC0M)
Traffic Class 0 is always routed to VC0.
0/1/0/MMR
114-117h
800000FFh
32 bits
RO; RW
Processor Configuration Registers
Description
Datasheet