CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 368

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.20.12
1.20.13
368
FEUADDR_REG - Fault Event Upper Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the interrupt message upper address. This register is treated as
RsvdZ by implementations reporting Extended Interrupt Mode (EIM) as not supported
in the Extended Capability register.
AFLOG_REG - Advanced Fault Log Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to specify the base address of memory-resident fault-log region.
This register is treated as read-only (0) for implementations not supporting advanced
translation fault logging (AFL field reported as 0 in the Capability register).
63:12
31:0
11:9
8:0
Bit
Bit
Access
Access
RO
RO
RO
RO
0000000
000000h
00000000h
Default
Value
000b
000h
Default
Value
Fault Log Address (FLA)
This field specifies the base of 4-KB aligned fault-log region in
system memory. Hardware ignores and not implement Bits
63:HAW, where HAW is the host address width.
Software specifies the base address and size of the fault log
region through this register, and programs it in hardware
through the SFL field in the Global Command register. When
implemented, reads of this field return the value that was last
programmed to it.
Fault Log Size (FLS)
This field specifies the size of the fault log region pointed to
by the FLA field. The size of the fault log region is (2^^X)*4-
KB, where X is the value programmed in this register.
When implemented, reads of this field return the value that
was last programmed to it.
Reserved
Message Upper Address (MUA)
Hardware implementations supporting Extended Interrupt
Mode are required to implement this register.
Hardware implementations not supporting Extended
Interrupt Mode may treat this field as RsvdZ.
0/2/0/GFXVTBAR
44-47h
00000000h
RO
32 bits
0/2/0/GFXVTBAR
58-5Fh
0000000000000000h
RO
64 bits
Processor Configuration Registers
Description
Description
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