CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 365

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.20.9
Datasheet
FECTL_REG - Fault Event Control Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the fault event interrupt message control bits. Section 7.3 describes
hardware handling of fault events.
Bit
31
Access
RW
Default
Value
1b
Interrupt Mask (IM)
0 = No masking of interrupts. When an interrupt condition is
1 = This is the value on reset. Software may mask interrupt
0/2/0/GFXVTBAR
38-3Bh
80000000h
RO; RW
32 bits
detected, hardware issues an interrupt message (using
the Fault Event Data & Fault Event Address register
values).
message generation by setting this field. Hardware is
prohibited from sending the interrupt message when
this field is set.
(Sheet 1 of 2)
Description
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