CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 367

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.20.10
1.20.11
Datasheet
FEDATA_REG - Fault Event Data Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the interrupt message data.
FEADDR_REG - Fault Event Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the interrupt message address.
31:16
15:0
31:2
1:0
Bit
Bit
Access
Access
RW
RW
RO
RO
Default
00000000h
Value
0000h
0000h
Default
Value
00b
Extended Interrupt Message Data (EID)
This field is valid only for implementations supporting 32-bit
interrupt data fields.
Hardware implementations supporting only 16-bit interrupt
data treat this field as RsvdZ.
Interrupt message data (ID)
Data value in the interrupt request.
Message Address (MA)
When fault events are enabled, the contents of this
register specify the DWORD-aligned address (bits 31:2)
for the interrupt request.
Reserved
0/2/0/GFXVTBAR
3C-3Fh
00000000h
RO; RW
32 bits
0/2/0/GFXVTBAR
40-43h
00000000h
RO; RW
32 bits
Description
Description
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