CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 93

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
31:27
21:20
Bit
26
25
24
23
22
Access
RW
RW
RW
RW
RW
RW
RW
Default
Value
06h
00b
0b
0b
0b
0b
0b
Rcomp Wait (RCOMPWAIT)
This configuration setting indicates the amount of
refresh_tick events to wait before the service of Rcomp
request in non-default mode of independent rank refresh.
Reserved
DRAM Refresh Hysteresis (REFHYSTERISIS)
Hysteresis level - Useful for dref_high watermark cases. The
dref_high flag is set when the dref_high watermark level is
exceeded, and is cleared when the refresh count is less than
the hysteresis level. This bit should be set to a value less
than the high watermark level.
This bit is used to enable the refresh counter to count
during times that DRAM is not in self-refresh, but refreshes
are not enabled. Such a condition may occur due to need to
reprogram SO-DIMMs following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e., there is
no mode where Refresh is enabled but the counter does not
run) so, in conjunction with Bit 23 REFEN, the modes are:
This configuration bit enables (by default) that all the ranks
are refreshed in a staggered/atomic fashion. If set, the
ranks are refreshed in an independent fashion.
0 = Ranks are refreshed atomically staggered
1 = Ranks are refreshed independently
Refresh is enabled.
0 = Disabled
1 = Enabled
Indicates that DDR initialization is complete.
All Rank Refresh (ALLRKREF)
Refresh Enable (REFEN)
DDR Initialization Done (INITDONE)
Refresh Counter Enable (REFCNTEN)
REFCNTEN
00:
01:
10:
11:
REFEN:
(Sheet 2 of 3)
0:0
0:1
1:X
3
4
5
6
Normal refresh disable
Refresh disabled, but
counter is accumulating
refreshes.
Normal refresh enable
Description
Description
93