CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 161

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.13.14
Datasheet
SSTS1 - Secondary Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
SSTS1 is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (i.e., PCI Express-G side) of the “virtual” PCI-to-PCI
bridge embedded within processor.
10:9
Bit
15
14
13
12
11
8
7
6
Access
RWC
RWC
RWC
RWC
RWC
RO
RO
RO
RO
Default
Value
00b
0b
0b
0b
0b
0b
0b
0b
0b
Detected Parity Error (DPE)
This bit is set by the Secondary Side for a Type 1
Configuration Space header device whenever it receives a
Poisoned TLP, regardless of the state of the Parity Error
Response Enable bit in the Bridge Control Register.
Received System Error (RSE)
This bit is set when the Secondary Side for a Type 1
configuration space header device receives an ERR_FATAL or
ERR_NONFATAL.
Received Master Abort (RMA)
This bit is set when the Secondary Side for Type 1
Configuration Space Header Device (for requests initiated by
the Type 1 Header Device itself) receives a Completion with
Unsupported Request Completion Status.
Received Target Abort (RTA)
This bit is set when the Secondary Side for Type 1
Configuration Space Header Device (for requests initiated by
the Type 1 Header Device itself) receives a Completion with
Completer Abort Completion Status.
Signaled Target Abort (STA)
Not Applicable or Implemented. Hard wired to 0. The
processor does not generate Target Aborts (the processor will
never complete a request using the Completer Abort
Completion status).
DEVSELB Timing (DEVT)
Not Applicable or Implemented. Hard wired to 0.
Master Data Parity Error (SMDPE)
When set indicates that the PROCESSOR received across the
link (upstream) a Read Data Completion Poisoned TLP
(EP=1). This bit can only be set when the Parity Error Enable
bit in the Bridge Control register is set.
Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hard wired to 0.
Reserved
0/1/0/PCI
1E-1Fh
0000h
RWC; RO
16 bits
(Sheet 1 of 2)
Description
161