CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 377

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.20.24
Datasheet
IEDATA_REG - Invalidation Completion Event Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the Invalidation Event interrupt message data. This register is
treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
31:16
29:0
15:0
Bit
Bit
30
Access
Access
RO
RO
RO
RO
00000000h
Default
Value
0000h
0000h
Default
Value
0b
Extended Interrupt Message Data (EIMD)
This field is valid only for implementations supporting 32-bit
interrupt data fields.
Hardware implementations supporting only 16-bit interrupt
data treat this field as RsvdZ.
Interrupt Message Data (IMD)
Data value in the interrupt request.
Interrupt Pending (IP)
Hardware sets the IP field whenever it detects an interrupt
condition. Interrupt condition is defined as:
An Invalidation Wait Descriptor with Interrupt Flag (IF)
field Set completed, setting the IWC field in the
Invalidation Completion Status register.
If the IWC field in the Invalidation Completion Status
register was already Set at the time of setting this field, it
is not treated as a new interrupt condition.
The IP field is kept Set by hardware while the interrupt
message is held pending. The interrupt message could be
held pending due to interrupt mask (IM field) being Set, or
due to other transient hardware conditions. The IP field is
cleared by hardware as soon as the interrupt message
pending condition is serviced. This could be due to either:
Hardware issuing the interrupt message due to either
change in the transient hardware condition that caused
interrupt message to be held pending or due to software
clearing the IM field.
Software servicing the IWC field in the Invalidation
Completion Status register.
Reserved
0/2/0/GFXVTBAR
A4-A7h
00000000h
RO
32 bits
(Sheet 2 of 2)
Description
Description
377