CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 352

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

352
Bit
3
2
1
0
Access
RO
RO
RO
RO
Default
Value
0b
0b
0b
0b
Interrupt Remapping (IR)
0 = Hardware does not support interrupt remapping.
1 = Hardware supports interrupt remapping.
Implementations reporting this field as Set must also
support Queued Invalidation (QI = 1b).
Device IOTLB Support (DI)
0 = Hardware does not support device-IOTLBs.
1 = Hardware supports Device-IOTLBs.
Implementations reporting this field as Set must also
support Queued Invalidation (QI = 1b).
Queued Invalidation (QI)
0 = Hardware does not support queued invalidations.
1 = Hardware supports queued invalidations.
Coherency (C)
This field indicates if hardware access to the root, context,
page-table and interrupt-remap structures are coherent
(snooped) or not.
0 = Indicates hardware accesses to remapping structures
1 = Indicates hardware accesses to remapping structures
Hardware access to advanced fault log and invalidation
queue is always coherent.
are incoherent.
are coherent.
(Sheet 2 of 2)
Processor Configuration Registers
Description
Datasheet