CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 379

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.20.27
Datasheet
IRTA_REG - Interrupt Remapping Table Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register providing the base address of Interrupt remapping table. This register is
treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not
supported in the Extended Capability register.
63:12
10:4
3:0
Bit
11
Access
RO
RO
RO
RO
0000000
000000h
Default
Value
00h
0b
0h
Reserved
Size (S)
This field specifies the size of the interrupt remapping table.
The number of entries in the interrupt remapping table is
2^^(X+1), where X is the value programmed in this field.
This field points to the base of 4-KB aligned interrupt
remapping table.
Hardware ignores and not implement Bits 63:HAW, where
HAW is the host address width.
Reads of this field returns value that was last programmed
to it.
0 = Legacy interrupt mode is active. Hardware interprets
1 = Intel® 64 platform is operating in Extended Interrupt
Hardware reporting Extended Interrupt Mode (EIM) as Clear
in the Capability register treats this field as RsvdZ.
Interrupt Remapping Table Address (IRTA)
Extended Interrupt Mode Enable (EIME)
only low 8 bits of Destination-ID field in the IRTEs. The
high 24 bits of the Destination-ID field is treated as
reserved. On Itanium™ platforms hardware interprets
the low 16 bits of the Destination-ID field in the IRTEs
and treats the high 16 bits as reserved.
Mode. Hardware interprets all 32 bits of the Destination-
ID field in the IRTEs.
0/2/0/GFXVTBAR
B8-BFh
0000000000000000h
RO
64 bits
Description
379