CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 104

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.9.28
104
C1CYCTRKWR - Channel 1 CYCTRK WR
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 1 CYCTRK WR
15:12
11:8
7:4
3:0
Bit
Access
RW
RW
RW
RW
Default
Value
0h
0h
0h
0h
ACT-to-Write Delay (C1sd_cr_act_wr)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the ACT and WRITE
commands to the same rank-bank.
Corresponds to tRCD_wr at DDR Spec.
Same Rank Write-to-Write Delayed (C1sd_cr_wrsr_wr)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two WRITE commands to
the same rank.
Different Rank Write-to-Write Delay
(C1sd_cr_wrdr_wr)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two WRITE commands to
different ranks. Corresponds to tWR_WR at DDR Spec.
READ-to-WRTE Delay (C1sd_cr_rd_wr)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the READ and WRITE
commands.
Corresponds to tRD_WR.
0/0/0/MCHBAR
656-657h
0000h
RW
16 bits
Processor Configuration Registers
Description
Datasheet