CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 244

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

244
15:8
6:4
3:1
Bit
7
0
Access
RW
RW
RO
RO
RO
Default
Value
000b
000b
00h
0b
0b
FLR, Core
FLR, Core
RST/
PWR
Core
Core
Core
Reserved
64 Bit Capable (64BCAP)
not implement the upper 32 bits of the Message
address register and is incapable of generating a
64-bit memory address.
This may need to change in future
implementations when addressable system
memory exceeds the 32b/4 GB limit.
Multiple Message Enable (MME)
System software programs this field to indicate
the actual number of messages allocated to this
device. This number is equal to or less than the
number actually requested.
The encoding is the same as for the MMC field
below.
Multiple Message Capable (MMC)
System Software reads this field to determine the
number of messages being requested by this
device.
All of the following are reserved in this
implementation
MSI Enable (MSIEN)
Controls the ability of this device to generate
MSIs.
hard wired to 0 to indicate that the function does
Value:Number of requests
000:1
001:2
010:4
011:8
100:16
101:32
110:Reserved
111:Reserved
Processor Configuration Registers
Description
Datasheet