CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 26

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.2.2.9
1.2.2.10
1.2.2.11
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APIC Configuration Space (FEC0_0000h-FECF_FFFFh)
This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in
the PCH portion of the chip-set, but may also exist as stand-alone components like
PXH.
The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that
may be populated in the system. Since it is difficult to relocate an interrupt controller
using plug-and-play software, fixed address decode regions have been allocated for
them. Processor accesses to the default IOAPIC region (FEC0_0000h to FEC7_FFFFh)
are always forwarded to DMI.
The GMCH optionally supports additional I/O APICs behind the PCI Express “Graphics”
port. When enabled via the PCI Express Configuration register (Device 1 Offset 200h)
the PCI Express port(s) will positively decode a subset of the APIC configuration space.
Specifically,
Memory requests to this range would then be forwarded to the PCI Express port. This
mode is intended for the entry Workstation/Server SKU of the GMCH, and would be
disabled in typical Desktop systems. When disabled, any access within entire APIC
Configuration space (FEC0_0000h to FECF_FFFFh) is forwarded to DMI.
MSI Interrupt Memory Space (FEE0_0000-FEEF_FFFF)
Any PCI Express or DMI device may issue a Memory Write to 0FEEx_xxxxh. This
Memory Write cycle does not go to DRAM. The GMCH will forward this Memory Write
along with the data to the CPU as an Interrupt Message Transaction.
This interrupt message is delivered to the CPU as an IntPhysical or IntLogical message.
High BIOS Area
For security reasons, the GMCH will now positively decode this range to DMI. This
positive decode will guarantee any overlapping ranges is ignored.
The top 2 MB (FFE0_0000h -FFFF_FFFFh) of the PCI Memory Address Range is reserved
for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the
system BIOS. The CPU begins execution from the High BIOS after reset. This region is
positively decoded to DMI Interface so that the upper subset of this region aliases to
16 MB–256 KB range. The actual address space required for the BIOS is less than 2 MB,
but the minimum CPU MTRR range for this region is 2 MB, so that full 2 MB must be
considered.
•
Device 1 can be enabled to claim FECC_0000h thru FECF_FFFFh.
Processor Configuration Registers
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