CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 96

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.9.16
96
C0ODTCTRL - Channel 0 ODT Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
13:10
31:12
9:1
11:8
Bit
7:4
3:0
Bit
0
Access
Access
RW
RW
RW
RW
RW
RW
RO
Default
00000h
Default
Value
Value
0FFh
0h
0h
0h
2h
0b
Reserved
DRAM ODT for Read Commands
(sd0_cr_odt_duration_rd)
Specifies the duration to assert DRAM ODT for Read
Commands. The Async value should be used when the
Dynamic Powerdown bit is set. Else use the Sync value.
DRAM ODT for Write Commands
(sd0_cr_odt_duration_wr)
Specifies the duration to assert DRAM ODT for Write
Commands. The Async value should be used when the
Dynamic Powerdown bit is set. Else use the Sync value.
MCH ODT for Read Commands
(sd0_cr_mchodt_duration)
Specifies the duration to assert MCH ODT for Read
Commands.
Minimum Power down Exit to Non-Read Command
Spacing (sd0_cr_txp)
This configuration register indicates the minimum number of
clocks to wait following assertion of CKE before issuing a
non-read command.
Self Refresh Exit Count (sd0_cr_slfrfsh_exit_cnt)
This configuration register indicates the Self refresh exit
count. (Program to 255).
Corresponds to the tXSNR/tXSRD parameters in the DDR3
Specification.
Only 1 DIMM Populated (sd0_cr_singledimmpop)
0: There is more than one DIMM or SO-DIMM in this channel
1: There is only one DIMM or SO-DIMM in this channel
Ah-Fh:Reserved.
2h-9h:2-9clocks.
0h-1h:Reserved.
0/0/0/MCHBAR
29C-29Fh
00000000h
RO; RW
32 bits
(Sheet 2 of 2)
Description
Processor Configuration Registers
Description
Datasheet