CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 197
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CP80617004119AES LBU3
Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet
1.CP80617004119AES_LBU3.pdf
(388 pages)
Specifications of CP80617004119AES LBU3
Lead Free Status / RoHS Status
Compliant
- Current page: 197 of 388
- Download datasheet (2Mb)
Processor Configuration Registers
1.13.45
Datasheet
RSTS - Root Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Provides information about PCI Express Root Complex specific parameters.
31:18
15:0
Bit
17
16
Access
RWC
RO
RO
RO
Default
Value
0000h
0000h
0b
0b
Reserved and Zero (RSVD)
For future R/WC/S implementations; software must use 0
for writes to bits.
PME Pending (PMEP)
Indicates that another PME is pending when the PME Status
bit is set. When the PME Status bit is cleared by software;
the PME is delivered by hardware by setting the PME Status
bit again and updating the Requestor ID appropriately. The
PME pending bit is cleared by hardware if no more PMEs are
pending.
PME Status (PMES)
Indicates that PME was asserted by the requestor ID
indicated in the PME Requestor ID field. Subsequent PMEs
are kept pending until the status register is cleared by
writing a 1 to this field.
PME Requestor ID (PMERID)
Indicates the PCI requestor ID of the last PME requestor.
0/1/0/PCI
C0-C3h
00000000h
RO; RWC
32 bits
Description
197
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