CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 76

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.8.30
76
SMICMD - SMI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register enables various errors to generate an SMI DMI special cycle. When an
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,
respectively. Note that one and only one message type can be enabled.
15:12
10:2
Bit
11
1
0
Access
RW
RW
RW
RO
RO
Default
Value
000h
0h
0b
0b
0b
1 = A SMI DMI special cycle is generated by GMCH when the
0 = Reporting of this condition via SMI messaging is
1 = The GMCH generates an SMI DMI message when it
0 = Reporting of this condition via SMI messaging is
1 = The GMCH generates an SMI DMI special cycle when the
0 = Reporting of this condition via SMI messaging is
Reserved
SMI on GMCH Thermal Sensor Trip (TSTSMI)
Reserved
SMI on Multiple-Bit DRAM ECC Error (DMESMI)
SMI on Single-bit ECC Error (DSESMI)
0/0/0/PCI
CC-CDh
0000h
16 bits
thermal sensor trip requires an SMI. A thermal sensor
trip point cannot generate more than one special cycle.
disabled.
detects a multiple-bit error reported by the DRAM
controller.
disabled. For systems not supporting ECC this bit must
be disabled.
DRAM controller detects a single bit error.
disabled. For systems that do not support ECC this bit
must be disabled.
RO; RW
Processor Configuration Registers
Description
Datasheet