CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 71

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.8.24
1.8.25
Datasheet
TSEGMB - TSEG Memory Base
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains the base address of TSEG DRAM memory. BIOS determines the
base of TSEG memory which must be at or below graphics GTT stolen base (PCI
Device 0 Offset A8 Bits 31:20).
Once D_LCK has been set, these bits becomes read only.
TOLUD - Top of Low Usable DRAM
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This 16-bit register defines the Top of Low Usable DRAM. TSEG, GTT Graphics memory
and Graphics Stolen Memory are within the DRAM space defined. From the top,
processor optionally claims 1 to 64 MBs of DRAM for internal graphics if enabled, 1 or
2 MB of DRAM for GTT Graphics Stolen Memory (if enabled) and 1, 2, or 8 MB of DRAM
for TSEG if enabled.
Programming Example:
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31:20
19:0
Bit
C1DRB3 is set to 4 GB
TSEG is enabled and TSEG size is set to 1 MB
Internal Graphics is enabled, and Graphics Mode Select is set to 32 MB
GTT Graphics Stolen Memory Size set to 2 MB
BIOS knows the OS requires 1 GB of PCI space.
BIOS also knows the range from 0_FEC0_0000h to 0_FFFF_FFFFh is not usable by
the system. This 20-MB range at the very top of addressable memory space is lost
to APIC and Intel TXT.
Access
RW-L
RO
Default
00000h
Value
000h
TESG Memory Base (TSEGMB)
This register contains Bits 31:20 of the base address of TSEG
DRAM memory. BIOS determines the base of TSEG memory
by subtracting the TSEG size (located within the CPU register
space) from graphics GTT stolen base (PCI Device 0 Offset A8
Bits 31:20).
Once D_LCK has been set, these bits become read only.
Reserved
0/0/0/PCI
AC-AFh
00000000h
RO; RW-L
32 bits
0/0/0/PCI
B0-B1h
0010h
RW-L; RO
16 bits
Description
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