CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 45

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.6
Datasheet
If the Bus Number is zero, the processor will generate a Type 0 Configuration Cycle TLP
on DMI. If the Bus Number is non-zero, and falls outside the range claimed by the
Host-PCI Express bridge, the processor will generate a Type 1 Configuration Cycle TLP
on DMI.
The PCH routes configurations accesses in a manner similar to the processor. The PCH
decodes the configuration TLP and generates a corresponding configuration access.
Accesses targeting a device on PCI Bus 0 may be claimed by an internal device. The
PCH compares the non-zero Bus Number with the Secondary Bus Number and
Subordinate Bus Number registers of its PCI-to-PCI bridges to determine if the
configuration access is meant for Primary PCI, or some other downstream PCI bus or
PCI Express link.
Configuration accesses that are forwarded to the PCH, but remain unclaimed by any
device or bridge will result in a master abort.
Processor Register Introduction
The processor contains two sets of software accessible registers, accessed via the Host
Processor I/O address space: Control registers and internal configuration registers.
The processor internal registers (I/O Mapped, Configuration and PCI Express Extended
Configuration registers) are accessible by the Host processor. The registers that reside
within the lower 256 bytes of each device can be accessed as Byte, Word (16 bit), or
Dword (32 bit) quantities, with the exception of CONFIG_ADDRESS, which can only be
accessed as a Dword. All multi-byte numeric fields use “little-endian” ordering (i.e.,
lower addresses contain the least significant parts of the field). Registers which reside
in bytes 256 through 4095 of each device may only be accessed using memory mapped
transactions in Dword (32 bit) quantities.
Some of the processor registers described in this section contain reserved bits. These
bits are labeled “Reserved”. Software must deal correctly with fields that are reserved.
On reads, software must use appropriate masks to extract the defined bits and not rely
on reserved bits being any particular value. On writes, software must ensure that the
values of reserved bit positions are preserved. That is, the values of reserved bit
positions must first be read, merged with the new values for other bit positions and
then written back. Note the software does not need to perform read, merge, and write
operation for the Configuration Address Register.
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Control registers are I/O mapped into the processor I/O space, which control
access to PCI and PCI Express configuration space (see section entitled I/O Mapped
Registers).
Internal configuration registers residing within the processor are partitioned into
three logical device register sets (“logical” since they reside within a single physical
device). The first register set is dedicated to Host Bridge functionality (i.e., DRAM
configuration, other chip-set operating parameters and optional features). The
second register block is dedicated to Host-PCI Express Bridge functions (controls
PCI Express interface configurations and operating parameters). The third register
block is for the internal graphics functions.
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