CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 38

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.2.9.1
38
Note:
The I/O accesses are forwarded normally to the DMI Interface bus unless they fall
within the PCI Express I/O address range as defined by the mechanisms explained
below. I/O writes are NOT posted. Memory writes to PCH or PCI Express are posted.
The PCI Express devices have a register that can disable the routing of I/O cycles to the
PCI Express device.
The GMCH responds to I/O cycles initiated on PCI Express or DMI with an UR status.
Upstream I/O cycles and configuration cycles should never occur. If one does occur, the
request will route as a read to Memory address 000C_0000h so a completion is
naturally generated (whether the original request was a read or write). The transaction
will complete with an UR completion status.
CPU I/O reads that lie within 8-byte boundaries but cross 4-byte boundaries are issued
from the CPU as 1 transaction. The GMCH will break this into 2 separate transactions.
I/O writes that lie within 8-byte boundaries but cross 4-byte boundaries is split into two
transactions by the CPU.
PCI Express I/O Address Mapping
The GMCH can be programmed to direct non-memory (I/O) accesses to the PCI
Express bus interface when CPU initiated I/O cycle addresses are within the PCI
Express I/O address range. This range is controlled via the I/O Base Address (IOBASE)
and I/O Limit Address (IOLIMIT) registers in GMCH Device 1 or Device 6 (if a second
PEG port is enabled) configuration space.
Address decoding for this range is based on the following concept. The top 4 bits of the
respective I/O Base and I/O Limit registers correspond to Address Bits A[15:12] of an
I/O address. For the purpose of address decoding, the GMCH assumes that lower 12
Address Bits A[11:0] of the I/O base are zero and that Address Bits A[11:0] of the I/O
limit address are FFFh. This forces the I/O address range alignment to 4-KB boundary
and produces a size granularity of 4 KB.
The GMCH positively decodes I/O accesses to PCI Express I/O address space as defined
by the following equation:
I/O_Base_Address  CPU I/O Cycle Address  I/O_Limit_Address
The effective size of the range is programmed by the plug-and-play configuration
software and it depends on the size of I/O space claimed by the PCI Express device.
The GMCH also forwards accesses to the Legacy VGA I/O ranges according to the
settings in the Device 1 configuration registers BCTRL (VGA Enable) and PCICMD1
(IOAE1), unless a second adapter (monochrome) is present on the DMI Interface/PCI
(or ISA). The presence of a second graphics adapter is determined by the MDAP
configuration bit. When MDAP is set, the GMCH will decode legacy monochrome IO
ranges and forward them to the DMI Interface. The I/O ranges decoded for the
monochrome adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh.
The GMCH Device 1 I/O address range registers defined above are used for all I/O
space allocation for any devices requiring such a window on PCI-Express. The PCICMD1
register can disable the routing of I/O cycles to PCI-Express.
Processor Configuration Registers
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