CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 81

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.9.2
Datasheet
CHDECMISC - Channel Decode Misc.
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
Enhanced addressing configuration bits.
6:5
Bit
7
4
Access
RW-L
RW-L
RO
Default
Value
00b
0b
0b
Enhanced Address for SO-DIMM Select
(ENHDIMMSEL)
This bit can be set when enhanced mode of addressing for
ranks is enabled and all four ranks are populated with equal
amount of memory.
0 = Use Standard methods for SO-DIMM Select.
1 = Use Enhanced Address as SO-DIMM Select.
This register is locked by Intel ME stolen Memory lock.
Enhanced Mode Select (ENHMODESEL)
This register is locked by Intel ME stolen Memory lock.
Reserved
00:Swap Enabled for Bank Selects and Rank Selects
01:XOR Enabled for Bank Selects and Rank Selects
10:Swap Enabled for Bank Selects only
11:XOR Enabled for Bank Select only
0/0/0/MCHBAR
111h
00h
RW-L; RO
8 bits
0h
(Sheet 1 of 2)
Encoding
Encoding
00b
01b
10b
11b
0b
1b
Description
Standard methods for SO-DIMM
Select
Enhanced Address as SO-DIMM
Select
Swap Enabled for Bank Selects and
Rank Selects
XOR Enabled for Bank Selects and
Rank Selects
Swap Enabled for Bank Selects only
XOR Enabled for Bank Select only
Description
Description
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