CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 284

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.18.21
1.18.22
284
IQA_REG - Invalidation Queue Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to configure the base address and size of the invalidation queue. This register
is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
When supported, writing to this register causes the Invalidation Queue Head and
Invalidation Queue Tail registers to be reset to 0h.
ICS_REG - Invalidation Completion Status Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to report completion status of invalidation wait descriptor with Interrupt Flag
(IF) Set. This register is treated as RsvdZ by implementations reporting Queued
Invalidation (QI) as not supported in the Extended Capability register.
63:12
31:1
11:3
Bit
2:0
Bit
0
Access
Access
RWC-P
RW
RW
RO
RO
00000000
00000000h
Default
00000h
Value
Default
000h
Value
0h
0b
Invalidation Queue Base Address (IQA)
This field points to the base of 4-KB aligned invalidation
request queue. Hardware ignores and not implement Bits
63:HAW, where HAW is the host address width. Reads of this
field return the value that was last programmed to it.
Reserved
Queue Size (QS)
This field specifies the size of the invalidation request queue.
A value of X in this field indicates an invalidation request
queue of (X+1) 4-KB pages. The number of entries in the
invalidation queue is 2
Reserved
Invalidation Wait Descriptor Complete (IWC)
Indicates completion of Invalidation Wait Descriptor with
Interrupt Flag (IF) field Set. Hardware implementations not
supporting queued invalidations implement this field as
RSVD.
0/0/0/VC0PREMAP
90-97h
0000000000000000h
RO; RW
64 bits
0/0/0/VC0PREMAP
9C-9Fh
00000000h
RO; RWC-P
32 bits
(X + 8)
Processor Configuration Registers
Description
Description
.
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