CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 346

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.20.1
1.20.2
346
VER_REG - Version Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to report the architecture version supported. Backward compatibility for the
architecture is maintained with new revision numbers, allowing software to load DMA-
remapping drivers written for prior architecture versions.
CAP_REG - Capability Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to report general DMA remapping hardware capabilities.
63:56
31:8
Bit
55
54
7:4
3:0
Bit
Access
Access
RO
RO
RO
RO
RO
RO
Default
Value
000000h
Default
00h
Value
1b
1b
1h
0h
Reserved
DMA Read Draining (DRD)
0 = On IOTLB invalidations, hardware does not support
1 = On IOTLB invalidations, hardware supports draining of
Indicates supported architecture version.
DMA Write Draining (DWD)
0 = On IOTLB invalidations, hardware does not support
1 = On IOTLB invalidations, hardware supports draining of
Reserved
Major Version Number (MAX)
Indicates supported architecture version.
Minor Version Number (MIN)
Indicates supported architecture minor version.
draining of translated DMA read requests queued within
the root complex.
translated DMA read requests queued within the root
complex.
draining of translated DMA writes queued within the root
complex.
translated DMA writes queued within the root complex.
0/2/0/GFXVTBAR
0-3h
00000010h
RO
32 bits
0/2/0/GFXVTBAR
8-Fh
00C0000020230272h
RO
64 bits
(Sheet 1 of 5)
Description
Processor Configuration Registers
Description
Datasheet