CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 92

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.9.13
1.9.14
92
C0CYCTRKREFR - Channel 0 CYCTRK REFR
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 0 CYCTRK Refresh Registers.
C0REFRCTRL - Channel 0 DRAM Refresh Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Settings to configure the DRAM refresh controller.
15:13
12:9
46:44
43:38
37:32
8:0
Bit
Bit
47
Access
Access
RW
RW
RO
RW
RW
RW
RO
Default
Default
Value
000b
000h
Value
010b
0h
10h
18h
0b
Reserved
Same Rank Precharge All to Refresh Delay
(C0sd_cr_pchgall_rfsh)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the PRE-ALL and REF
commands to the same rank.
Same Rank Refresh to Refresh Delay
(C0sd_cr_rfsh_rfsh)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two REF commands to the
same rank.
Reserved
Initial Refresh Count (INITREFCNT)
Initial Refresh Count Value
Direct Rcomp Quiet Window (DIRQUIET)
This configuration setting indicates the amount of
refresh_tick events to wait before the service of Rcomp
request in non-default mode of independent rank refresh.
Indirect Rcomp Quiet Window (INDIRQUIET)
This configuration setting indicates the amount of
refresh_tick events to wait before the service of Rcomp
request in non-default mode of independent rank refresh.
0/0/0/MCHBAR
25B-25Ch
0000h
RO; RW
16 bits
0/0/0/MCHBAR
269-26Eh
241830000C30h
RO; RW
48 bits
(Sheet 1 of 3)
Processor Configuration Registers
Description
Description
Datasheet