CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 349

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
Bit
7
6
5
4
3
Access
RO
RO
RO
RO
RO
Default
Value
0b
1b
1b
1b
0b
Caching Mode (CM)
0 = Not-present and erroneous entries are not cached in any
1 = Not-present and erroneous mappings may be cached in
Hardware implementations of this architecture must support a
value of 0 in this field. Refer to Section 6.1 for more details on
Caching Mode.
Protected High-Memory Region (PHMR)
0 = Indicates protected high-memory region is not supported.
1 = Indicates protected high-memory region is supported.
DMA-remapping hardware implementations on Intel VT-d
platforms supporting main memory above 4 GB are required
to support protected high-memory region.
Protected Low-Memory Region (PLMR)
0 = Indicates protected low-memory region is not supported.
1 = Indicates protected low-memory region is supported.
DMA-remapping hardware implementations on Intel TXT
platforms are required to support protected low-memory
region.
Required Write-Buffer Flushing (RWBF)
0 = Indicates no write-buffer flushing is needed to ensure
1 = Indicates software must explicitly flush the write buffers
Advanced Fault Logging (AFL)
0 = Indicates advanced fault logging is not supported. Only
1 = Indicates advanced fault logging is supported.
of the remapping caches. Invalidations are not required
for modifications to individual not present or invalid
entries. However, any modifications that result in
decreasing the effective permissions or partial permission
increases require invalidations for them to be effective.
the remapping caches. Any software updates to the
remapping structures (including updates to “not present”
or erroneous entries) require explicit invalidation.
changes to memory-resident structures are visible to
hardware.
to ensure updates made to memory-resident remapping
structures are visible to hardware. Refer to Section 11.1
for more details on write buffer flushing requirements.
primary fault logging is supported.
(Sheet 4 of 5)
Description
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