CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 341

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.19.30
Datasheet
FRCD_REG - Fault Recording Registers
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Registers to record fault information when primary fault logging is active. Hardware
reports the number and location of fault recording registers through the Capability
register. This register is relevant only for primary fault logging.
These registers are sticky and can be cleared only through powergood reset or via
software clearing the RWC fields by writing a 1.
125:124
123:104
103:96
95:80
127
126
Bit
Access
RWC-P
RO-P
RO-P
RO-P
RO
RO
Default
00000h
Value
0000h
00b
00h
0b
0b
Fault (F)
Hardware sets this field to indicate a fault is logged in this
Fault Recording register. The F field is Set by hardware after
the details of the fault is recorded in other fields.
When this field is Set, hardware may collapse additional
faults from the same source-id (SID).
Software writes the value read from this field to Clear it.
Refer to Intel VT-d specification Section 7.2.1 for hardware
details of primary fault logging.
Type (T)
Type of the faulted request:
0 = Write request
1 = Read request
This field is relevant only when the F field is Set, and when
the fault reason (FR) indicates one of the DMA-remapping
fault conditions.
Address Type (AT)
This field captures the AT field from the faulted DMA
request. Hardware implementations not supporting Device-
IOTLBs (DI field Clear in Extended Capability register) treat
this field as RsvdZ.
When supported, this field is valid only when the F field is
Set, and when the fault reason (FR) indicates one of the
DMA-remapping fault conditions.
Reserved
Fault Reason (FR)
Reason for the fault. Intel VT-d specification Appendix A
enumerates the various translation fault reason encodings.
This field is relevant only when the F field is set.
Reserved
0/0/0/DMIVC1REMAP
200-20Fh
00000000000000000000000000000000h
RWC-P; RO-P; RO
128 bits
(Sheet 1 of 2)
Description
341