CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 236

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.16.17
1.16.18
1.16.19
236
INTRLINE - Interrupt Line
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
INTRPIN - Interrupt Pin
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
MINGNT - Minimum Grant
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
7:0
7:0
7:0
Bit
Bit
Bit
Access
Access
Access
RW
RO
RO
Default
Default
Default
Value
Value
Value
00h
00h
01h
Minimum Grant Value (MGV)
The IGD does not burst as a PCI-compliant master.
Interrupt Connection (INTCON)
Used to communicate interrupt line routing information. POST
software writes the routing information into this register as it
initializes and configures the system. The value in this
register indicates to which input of the system interrupt
controller the device's interrupt pin is connected.
Interrupt Pin (INTPIN)
As a single function device, the IGD specifies INTA# as its
interrupt pin.
01h:INTA#.
0/2/0/PCI
3Ch
00h
RW
8 bits
0/2/0/PCI
3Dh
01h
RO
8 bits
0/2/0/PCI
3Eh
00h
RO
8 bits
Description
Description
Processor Configuration Registers
Description
Datasheet