CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 249

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.16.35
Datasheet
GSE - Graphics System Event Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:24
23:16
15:8
7:0
Bit
Access
RW
RW
RW
RW
Default
Value
00h
00h
00h
00h
GSE Scratch Trigger 3 (AST3)
When written, this scratch byte triggers an interrupt when
IER Bit 0 is enabled and IMR bit 0 is unmasked. If written as
part of a 16-bit or 32-bit write, only one interrupt is
generated in common.
GSE Scratch Trigger 2 (AST2)
When written, this scratch byte triggers an interrupt when
IER Bit 0 is enabled and IMR bit 0 is unmasked. If written as
part of a 16-bit or 32-bit write, only one interrupt is
generated in common.
GSE Scratch Trigger 1 (AST1)
When written, this scratch byte triggers an interrupt when
IER Bit 0 is enabled and IMR bit 0 is unmasked. If written as
part of a 16-bit or 32-bit write, only one interrupt is
generated in common.
GSE Scratch Trigger 0 (AST0)
When written, this scratch byte triggers an interrupt when
IER Bit 0 is enabled and IMR bit 0 is unmasked. If written as
part of a 16-bit or 32-bit write, only one interrupt is
generated in common.
0/2/0/PCI
E4-E7h
00000000h
RW
32 bits
Description
249