CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 54

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.8.7
1.8.8
1.8.9
54
MLT - Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Device 0 in the processor is not a PCI master. Therefore this register is not
implemented.
HDR - Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register identifies the header layout of the configuration space. No physical
register exists at this location.
SVID - Subsystem Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This value is used to identify the vendor of the subsystem.
15:0
7:0
7:0
Bit
Bit
Bit
Access
Access
Access
RW-O
RO
RO
Default
Default
Default
0000h
Value
Value
Value
00h
00h
Reserved
PCI Header (HDR)
This field always returns 0 to indicate that the processor is a
single function device with standard header layout. Reads
and writes to this location have no effect.
Subsystem Vendor ID (SUBVID)
This field should be programmed during boot-up to indicate
the vendor of the system board. After it has been written
once, it becomes read only.
0/0/0/PCI
Dh
00h
RO
8 bits
0/0/0/PCI
Eh
00h
RO
8 bits
0/0/0/PCI
2C-2Dh
0000h
RW-O
16 bits
Processor Configuration Registers
Description
Description
Description
Datasheet