CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 133

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.10.16
1.10.17
Datasheet
MCHTSWDT - Memory Controller Thermal Sensor Watch
Dog Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
When thermally hot tripped and memory controller throttling is enabled, this register
allows the value in the TSWDT0[Delta] field to affect the impact of the MCHETT[PEWAT]
whenever the MCHTSWDT WDT times outs.
MEMTDPCTW - Memory TDP Controller Registers
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
28:21
19:16
31:24
23:16
15:8
15:8
7:5
3:0
7:3
2:0
Bit
Bit
31
30
29
20
4
Access
Access
RWC
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
Default
Default
Value
0000b
Value
000b
000b
00h
00h
00h
00h
00h
00h
0b
0b
0b
0b
0b
0h
Enable WDT (ENWDT)
0 = WDT function is not enabled. WDT has no impact to
1 = WDT function is enabled.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0/0/0/MCHBAR
12D0-12D3h
00000000h
RO; RW; RWC
32 bits
0/0/0/MCHBAR
2D4-2D7h
00000000h
32 bits
Reserved
RO; RW
throttling.
Description
Description
133