CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 59

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
11:8
Bit
Access
RW-L
Default
Value
0h
GTT Graphics Memory Size (GGMS)
This field is used to select the amount of main memory that
is pre-allocated to support the internal graphics translation
table. The BIOS ensures that memory is pre-allocated only
when internal graphics is enabled.
GSM is assumed to be a contiguous physical DRAM space
with DSM, and BIOS needs to allocate a contiguous memory
chunk. Hardware will drive the base of GSM from DSM only
using the GSM size programmed in the register.
0h: No memory pre-allocated. GTT cycles (Mem and IO) are
not claimed.
1h: No Intel® Virtualization Technology (Intel® VT-d) mode,
1 MB of memory pre-allocated for GTT.
3h: No Intel VT-d mode, 2 MB of memory pre-allocated for
GTT.
9h: Intel VT-d mode, 2 MB of memory pre-allocated for 1 MB
of Global GTT and 1 MB for Shadow GTT.
Ah: Intel VT-d mode, 3 MB of memory pre-allocated for
1.5 MB of Global GTT and 1.5 MB for Shadow GTT.
Bh: Intel VT-d mode, 4 MB of memory pre-allocated for 2 MB
of Global GTT and 2 MB for Shadow GTT.
All unspecified encoding of this register field are reserved,
hardware functionality is not guaranteed if used. This
register is locked and becomes Read Only when the D_LCK
bit in the SMRAM register is set.
Encoding
(Sheet 2 of 4)
3h
1h
0h
9h
Ah
Bh
No Intel VT -d mode, 2
MB
No Intel VT -d mode, 1
MB
No memory preallocated
Intel VT -d mode, 2 MB
Intel VT -d mode, 3 MB
Intel VT -d mode, 4 MB
Description
Description
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