CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 4

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

4
1.9
1.10
1.8.26 PBFC - Primary Buffer Flush Control ..........................................................73
1.8.27 SBFC - Secondary Buffer Flush Control ......................................................73
1.8.28 ERRSTS - Error Status .............................................................................74
1.8.29 ERRCMD - Error Command.......................................................................75
1.8.30 SMICMD - SMI Command.........................................................................76
1.8.31 SCICMD - SCI Command .........................................................................77
1.8.32 SKPD - Scratchpad Data ..........................................................................77
1.8.33 CAPID0 - Capability Identifier ...................................................................78
Device 0 MCHBAR DRAM Controls ........................................................................78
1.9.1
1.9.2
1.9.3
1.9.4
1.9.5
1.9.6
1.9.7
1.9.8
1.9.9
1.9.10 C0CYCTRKACT - Channel 0 CYCTRK ACT ....................................................89
1.9.11 C0CYCTRKWR - Channel 0 CYCTRK WR......................................................90
1.9.12 C0CYCTRKRD - Channel 0 CYCTRK READ ...................................................91
1.9.13 C0CYCTRKREFR - Channel 0 CYCTRK REFR.................................................92
1.9.14 C0REFRCTRL - Channel 0 DRAM Refresh Control .........................................92
1.9.15 C0CKECTRL - Channel 0 CKE Control .........................................................95
1.9.16 C0ODTCTRL - Channel 0 ODT Control ........................................................96
1.9.17 C0DTC - Channel 0 DRAM Throttling Control...............................................97
1.9.18 C0DTPEW - Channel 0 DRAM Rank Throttling Passive Event..........................98
1.9.19 C0DTAEW - Channel 0 DRAM Rank Throttling Active Event ...........................99
1.9.20 C1DRB0 - Channel 1 DRAM Rank Boundary Address 0 .................................99
1.9.21 C1DRB1 - Channel 1 DRAM Rank Boundary Address 1 ............................... 100
1.9.22 C1DRB2 - Channel 1 DRAM Rank Boundary Address 2 ............................... 100
1.9.23 C1DRB3 - Channel 1 DRAM Rank Boundary Address 3 ............................... 101
1.9.24 C1DRA01 - Channel 1 DRAM Rank 0,1 Attributes....................................... 101
1.9.25 C1DRA23 - Channel 1 DRAM Rank 2,3 Attributes....................................... 102
1.9.26 C1CYCTRKPCHG - Channel 1 CYCTRK PCHG ............................................. 102
1.9.27 C1CYCTRKACT - Channel 1 CYCTRK ACT .................................................. 103
1.9.28 C1CYCTRKWR - Channel 1 CYCTRK WR.................................................... 104
1.9.29 C1CYCTRKRD - Channel 1 CYCTRK READ ................................................. 105
1.9.30 C1CKECTRL - Channel 1 CKE Control ....................................................... 106
1.9.31 C1REFRCTRL - Channel 1 DRAM Refresh Control ....................................... 107
1.9.32 C1ODTCTRL - Channel 1 ODT Control ...................................................... 110
1.9.33 C1DTC - Channel 1 DRAM Throttling Control............................................. 111
1.9.34 C1DTPEW - Channel 1 DRAM Rank Throttling Passive Event........................ 112
1.9.35 C1DTAEW - Channel 1 DRAM Rank Throttling Active Event ......................... 113
1.9.36 DDRMPLL1 - DDR PLL BIOS .................................................................... 114
Device 0 MCHBAR Thermal Management Controls ................................................ 114
1.10.1 TSC1 - Thermal Sensor Control 1 ............................................................ 116
1.10.2 TSS1 - Thermal Sensor Status 1 ............................................................. 117
1.10.3 TR1 - Thermometer Read 1 .................................................................... 118
1.10.4 TOF1 - Thermometer Offset 1................................................................. 119
1.10.5 RTR1 - Relative Thermometer Read 1 ...................................................... 119
1.10.6 TSTTPA1 - Thermal Sensor Temperature Trip Point A1 ............................... 120
1.10.7 TSTTPB1 - Thermal Sensor Temperature Trip Point B1 ............................... 121
CSZMAP - Channel Size Mapping...............................................................80
CHDECMISC - Channel Decode Misc. .........................................................81
C0DRB0 - Channel 0 DRAM Rank Boundary Address 0 .................................83
C0DRB1 - Channel 0 DRAM Rank Boundary Address 1 .................................84
C0DRB2 - Channel 0 DRAM Rank Boundary Address 2 .................................84
C0DRB3 - Channel 0 DRAM Rank Boundary Address 3 .................................85
C0DRA01 - Channel 0 DRAM Rank 0,1 Attribute ..........................................85
C0DRA23 - Channel 0 DRAM Rank 2,3 Attribute ..........................................87
C0CYCTRKPCHG - Channel 0 CYCTRK PCHG ...............................................88
Datasheet