CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 183

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
17:15
14:12
11:10
9:4
Bit
Access
RW-O
RW-O
RW-O
RO
if x16
device is
present
if x8 device
is present
or in
bifurcation
mode
Default
Value
010b
100b
11b
10h
08h
L1 Exit Latency (L1ELAT)
Indicates the length of time this Port requires to complete
the transition from L1 to L0.
000: Less than 1us
001: 1 us to less than 2 us
010: 2 us to less than 4 us
011: 4 us to less than 8 us
100: 8 us to less than 16 us
101: 16 us to less than 32 us
110: 32 us-64 us
111: More than 64 us
BIOS Requirement: If this field is required to be any
value other than the default, BIOS must initialize it
accordingly.
Both bytes of this register that contain a portion of this
field must be written simultaneously in order to prevent
an intermediate (and undesired) value from ever existing.
L0s Exit Latency (L0SELAT)
Indicates the length of time this Port requires to complete
the transition from L0s to L0.
000:Less than 64 ns
001:64 ns to less than 128 ns
010:128 ns to less than 256 ns
011:256 ns to less than 512 ns
100:512 ns to less than 1 µs
101:1 µs to less than 2 µs
110:2 µs - 4 µs
111:More than 4 µs
The actual value of this field depends on the common
Clock Configuration bit (LCTL[6]) register.
Active State Link PM Support (ASLPMS)
ASPM L0s and L1 supported.
Max Link Width (MLW)
Indicates the maximum number of lanes supported for
this link.
(Sheet 3 of 4)
Description
183