CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 163

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.13.17
Datasheet
Note:
software. For the purpose of address decode address bits A[19:0] are assumed to be
FFFFFh. Thus, the top of the defined memory address range is at the top of a 1-MB
aligned memory block.
Memory range covered by MBASE and MLIMIT registers are used to map non-
prefetchable PCI Express-G address ranges (typically where control/status memory-
mapped I/O data structures of the graphics controller will reside) and PMBASE and
PMLIMIT are used to map prefetchable address ranges (typically graphics local
memory). This segregation allows application of USWC space attribute to be performed
in a true plug-and-play manner to the prefetchable address range for improved CPU-
PCI Express memory access performance.
Note also that configuration software is responsible for programming all address range
registers (prefetchable, non-prefetchable) with the values that provide exclusive
address ranges, i.e., prevent overlap with each other and/or with the ranges covered
with the main memory. There is no provision in the processor hardware to enforce
prevention of overlap and operations of the system in the case of overlap are not
guaranteed.
PMBASE1 - Prefetchable Memory Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register in conjunction with the corresponding Upper Base Address register
controls the CPU to PCI Express-G prefetchable memory access routing based on the
following formula:
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range is aligned to a 1-MB boundary.
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
15:4
3:0
Bit
Access
RW
RO
Default
Value
000h
0h
Memory Address Limit (MLIMIT)
Corresponds to A[31:20] of the upper limit of the address
range passed to PCI Express-G.
Reserved
0/1/0/PCI
24-25h
FFF1h
RO; RW
16 bits
Description
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