CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 191
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CP80617004119AES LBU3
Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet
1.CP80617004119AES_LBU3.pdf
(388 pages)
Specifications of CP80617004119AES LBU3
Lead Free Status / RoHS Status
Compliant
- Current page: 191 of 388
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Processor Configuration Registers
1.13.42
Datasheet
SLOTCTL - Slot Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
PCI Express Slot related registers allow for the support of Hot Plug.
15:13
Bit
12
11
10
Access
RO
RO
RO
RO
Default
Value
000b
0b
0b
0b
Reserved
Reserved for Data Link Layer State Changed Enable
(DLLSCE)
If the Data Link Layer Link Active capability is implemented,
when set to 1b, this field enables software notification when
Data Link Layer Link Active field is changed.
If the Data Link Layer Link Active capability is not
implemented, this bit is permitted to be read-only with a
value of 0b.
Reserved for Electromechanical Interlock Control (EIC)
If an Electromechanical Interlock is implemented, a write of
1b to this field causes the state of the interlock to toggle. A
write of 0b to this field has no effect. A read to this register
always returns a 0.
Reserved for Power Controller Control (PCC)
If a Power Controller is implemented, this field when written
sets the power state of the slot per the defined encodings.
Reads of this field must reflect the value from the latest write,
even if the corresponding hot-plug command is not complete,
unless software issues a write without waiting for the
previous command to complete in which case the read value
is undefined.
Depending on the form factor, the power is turned on/off
either to the slot or within the adapter. Note that in some
cases the power controller may autonomously remove slot
power or not respond to a power-up request based on a
detected fault condition, independent of the Power Controller
Control setting.
The defined encodings are:
0b Power On
1b Power Off
If the Power Controller Implemented field in the Slot
Capabilities register is set to 0b, then writes to this field have
no effect and the read value of this field is undefined.
0/1/0/PCI
B8-B9h
0000h
RO; RW
16 bits
(Sheet 1 of 3)
Description
191
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