CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 351

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.20.3
Datasheet
ECAP_REG - Extended Capability Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to report DMA-remapping hardware extended capabilities.
63:24
23:20
19:18
17:8
Bit
7
6
5
4
Access
RO
RO
RO
RO
RO
RO
RO
RO
00000000
Default
Value
010h
00h
00b
0h
0b
0b
0b
0b
Reserved
Maximum Handle Mask Value (MHMV)
The value in this field indicates the maximum supported
value for the Handle Mask (HM) field in the interrupt entry
cache invalidation descriptor (iec_inv_dsc).
This field is valid only when the IR field is reported as Set.
Reserved
Invalidation Unit Offset (IVO)
This field specifies the offset to the IOTLB invalidation
register relative to the register base address of this
remapping hardware unit.
If the register base address is X, and the value reported in
this field is Y, the address for the IOTLB invalidation register
is calculated as X+(16*Y).
Snoop Control (SC)
0 = Hardware does not support setting the SNP field to 1 in
1 = Hardware supports setting the SNP field to 1 in the
Pass Through (PT)
0 = Hardware does not support pass through translation
1 = Hardware supports pass-through translation type in
Caching Hints (CH)
0 = Hardware does not support IOTLB caching hints (ALH
1 = Hardware supports IOLTB caching hints through the ALH
0 = Hardware supports only 8-bit APICIDs (Legacy
1 = Hardware supports Extended Interrupt Mode (32-bit
This field is valid only when the IR field is reported as Set.
Extended Interrupt Mode (EIM)
0/2/0/GFXVTBAR
10-17h
0000000000001000h
RO
64 bits
the page-table entries.
page-table entries.
type in context entries.
context entries.
and EH fields in context-entries are treated as
reserved).
and EH fields in context-entries.
Interrupt Mode) on Intel®64 and IA-32 platforms and
16-bit APIC-IDs on Itanium platforms.
APIC-IDs) on Intel®64 platforms.
(Sheet 1 of 2)
Description
351