CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 173

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CP80617004119AES LBU3

Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet

Specifications of CP80617004119AES LBU3

Lead Free Status / RoHS Status
Compliant
Processor Configuration Registers
1.13.27
1.13.28
Datasheet
SS_CAPID - Subsystem ID and Vendor ID Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This capability is used to uniquely identify the subsystem where the PCI device resides.
Because this device is an integrated part of the system and not an add-in device, it is
anticipated that this capability will never be used. However, it is necessary because
Microsoft will test for its presence.
SS - Subsystem ID and Subsystem Vendor ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
System BIOS can be used as the mechanism for loading the SSID/SVID values. These
values must be preserved through power management transitions and a hardware
reset.
31:16
31:16
15:8
15:0
7:0
Bit
Bit
Access
Access
RW-O
RW-O
RO
RO
RO
Default
Default
0000h
8086h
Value
0000h
Value
0Dh
80h
Subsystem ID (SSID)
Identifies the particular subsystem and is assigned by the
vendor.
Subsystem Vendor ID (SSVID)
Identifies the manufacturer of the subsystem and is the same
as the vendor ID which is assigned by the PCI Special Interest
Group.
Reserved
Pointer to Next Capability (PNC)
This contains a pointer to the next item in the capabilities list
which is the PCI Power Management capability.
Capability ID (CID)
Value of 0Dh identifies this linked list item (capability
structure) as being for SSID/SSVID registers in a PCI-to-PCI
Bridge.
0/1/0/PCI
88-8Bh
0000800Dh
RO
32 bits
0/1/0/PCI
8C-8Fh
00008086h
RW-O
32 bits
Description
Description
173

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