CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 27

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.2.3
Datasheet
Main Memory Address Space (4 GB to TOUUD)
The processor supports 36-bit addressing. The maximum main memory size supported
is 16GB total DRAM memory. A hole between TOLUD and 4 GB occurs when main
memory size approaches 4 GB or larger. As a result, TOM, and TOUUD registers and
REMAPBASE/REMAPLIMIT registers become relevant.
The remap configuration registers exist to remap lost main memory space. The greater
than 32-bit remap handling is handled similar to other GMCHs.
Upstream read and write accesses above 36-bit addressing is treated as invalid cycles
by PEG and DMI.
Top of Memory (TOM)
The “Top of Memory” (TOM) register reflects the total amount of populated physical
memory. This is NOT necessarily the highest main memory address (holes may exist in
main memory address map due to addresses allocated for memory mapped IO above
TOM).
Intel ME stolen size register reflects the total amount of physical memory stolen by the
Manageability Engine. Intel ME stolen memory is located at the top of physical memory.
Intel ME stolen memory base is calculated by subtracting the amount of memory stolen
by the Manageability Engine from TOM.
Top of Upper Usable DRAM (TOUUD)
The Top of Upper Usable Dram (TOUUD) register reflects the total amount of
addressable DRAM. If remap is disabled, TOUUD will reflect TOM minus Manageability
Engine's stolen size. If remap is enabled, then it will reflect the remap limit. Note, when
there is more then 4 GB of DRAM and reclaim is enabled, the reclaim base is the same
as TOM minus Intel ME stolen memory size to the nearest 64-MB alignment (shown in
case 2 below).
Top of Low Usable DRAM (TOLUD)
TOLUD register is restricted to 4 GB memory (A[31:20]), but the processor can support
up to 16 GB, limited by DRAM pins. For physical memory greater than 4 GB, the TOUUD
register helps identify the address range in between the 4-GB boundary and the top of
physical memory. This identifies memory that can be directly accessed (including
remap address calculation) which is useful for memory access indication and early path
indication. When remap is enabled, TOLUD must be 64-MB aligned, but when remap is
disabled, TOLUD can be 1 MB aligned.
TSEG_BASE
The “TSEG_BASE” register reflects the total amount of low addressable DRAM, below
TOLUD. BIOS will calculate and program this register, so the GMCH has knowledge of
where (TOLUD)-(Gfx stolen)-(Gfx GTT stolen)-(TSEG) is located. IO blocks use this
minus DPR for upstream DRAM decode.
27