CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 371

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.20.16
Datasheet
PLMLIMIT_REG - Protected Low Memory Limit Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to set up the limit address of DMA-protected low-memory region below 4 GB.
This register must be set up before enabling protected memory through PMEN_REG,
and must not be updated when protected memory regions are enabled.
When the LT CMD.LOCK.PMRC command is invoked, this register is locked (treated as
RO). When the LT CMD.UNLOCK. PMRC command is invoked, this register is unlocked
(treated as RW).
This register is always treated as RO for implementations not supporting protected low
memory region (PLMR field reported as 0 in the capability register).
The alignment of the protected low memory region limit depends on the number of
reserved bits (N:0) of this register. Software may determine N by writing all 1’s to this
register, and finding most significant zero bit position with 0 in the value read back
from the register. Bits N:0 of the limit register are decoded by hardware as all 1s.
The Protected low-memory base and limit registers function as follows:
•
•
31:21
20:0
Bit
Programming the protected low-memory base and limit registers the same value in
Bits 31:(N+1) specifies a protected low-memory region of size 2
Programming the protected low-memory limit register with a value less than the
protected low-memory base register disables the protected low-memory region.
Access
RW
RO
000000h
Default
Value
000h
Protected Low-Memory Limit (PLML)
This register specifies the last host physical address of the
DMA-protected low-memory region in system memory.
Reserved
0/2/0/GFXVTBAR
6C-6Fh
00000000h
RO; RW
32 bits
Description
(N+1)
bytes.
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