CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 61

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
Bit
1
0
Access
RW-L
RO
Default
Value
0b
0b
IGD VGA Disable (IVD)
0 = Enable. Device 2 (IGD) claims VGA memory and IO
1 = Disable. Device 2 (IGD) does not claim VGA cycles (Mem
BIOS Requirement: BIOS must not set this bit to 0 if the
GMS field (Bits 6:4 of this register) pre-allocates no
memory. This bit MUST be set to 1 if Device 2 is disabled via
register (DEVEN[3] = 0).
This register is locked by Intel VT-d.
Reserved
Encoding
cycles, the Sub-Class Code within Device 2 Class Code
register is 00.
and IO), and the Sub- Class Code field within Device 2
function 0 Class Code register is 80.
(Sheet 4 of 4)
0b
1b
Description
Description
Disable
Enable
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