CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 267

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.18.6
Datasheet
RTADDR_REG - Root-Entry Table Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register providing the base address of root-entry table.
22:0
63:12
11:0
Bit
23
Bit
Access
Access
RO
RO
RW
RO
0000000
000000h
Default
000000h
Default
Value
Value
000h
0b
Root Table Address (RTA)
This register points to base of page aligned
4-KB-sized root-entry table in system memory.
Hardware may ignore and not implement Bits 63:HAW, where
HAW is the host address width.
Software specifies the base address of the root-entry table
through this register, and programs it in hardware through the
SRTP field in the Global Command register. Reads of this
register returns value that was last programmed to it.
Reserved
Compatibility Format Interrupt Status (CFIS)
This field indicates the status of Compatibility format
interrupts on Intel®64 implementations supporting interrupt-
remapping. The value reported in this field is applicable only
when interrupt-remapping is enabled and Legacy interrupt
mode is active.
0 = Compatibility format interrupts are blocked.
1 = Compatibility format interrupts are processed as pass-
Reserved
through (bypassing interrupt remapping).
0/0/0/VC0PREMAP
20-27h
0000000000000000h
RO; RW
64 bits
(Sheet 3 of 3)
Description
Description
267