CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 340

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

340
47:32
31:0
Bit
49
48
Access
RW
RW
RW
RO
00000000h
Default
0000h
Value
0b
0b
Drain Reads (DR)
This field is ignored by hardware if the DRD field is reported
as clear in the Capability register.
When DRD field is reported as set in the Capability register,
the following encodings are supported for this field:
0 = Hardware may complete the IOTLB invalidation without
1 = Hardware must drain all/relevant translated DMA reads
Refer to Intel VT-d specification section 6.3 for description
of DMA draining.
Drain Writes (DW)
This field is ignored by hardware if the DWD field is
reported as clear in the Capability register.
When DWD field is reported as set in the Capability register,
the following encodings are supported for this field:
0 = Hardware may complete the IOTLB invalidation without
1 = Hardware must drain all/relevant translated DMA writes
Refer to Intel VT-d specification section 6.3 for description
of DMA draining.
Domain-ID (DID)
Indicates the ID of the domain whose IOTLB entries need to
be selectively invalidated. This field must be programmed
by software for domain-selective and domain-page-
selective invalidation requests.
The Capability register reports the domain-id width
supported by hardware. Software must ensure that the
value written to this field is within this limit.
Hardware may ignore and not implement bits 47:(32+N)
where N is the supported domain-id width reported in the
capability register.
Reserved
(Sheet 3 of 3)
draining any translated DMA reads that are queued in
the root-complex and yet to be processed.
that are queued in the root-complex before indicating
IOTLB invalidation completion to software.
draining any translated DMA writes that are queued in
the root-complex for processing.
that are queued in the root-complex before indicating
IOTLB invalidation completion to software.
Processor Configuration Registers
Description
Datasheet