CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 129

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.10.13
Datasheet
TSCICMD - Thermal SCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register selects specific errors to generate a SCI DMI cycle, as enabled by the SCI
Error Command Register [SCI on Thermal Sensor Trip]. The SCI and SERR must not be
enabled at the same time for the thermal sensor event.
7:6
Bit
5
4
3
2
1
0
Access
RW
RW
RW
RW
RW
RW
RO
Default
Value
00b
0b
0b
0b
0b
0b
0b
Reserved
SCI on Catastrophic Thermal Sensor Trip (CATSCI)
0 = Disable reporting of this condition via SCI messaging.
1 = Does not mask the generation of an SCI DMI cycle on a
SCI on Hot Thermal Sensor Trip (HOTSCI)
0 = Disable reporting of this condition via SCI messaging.
1 = Does not mask the generation of an SCI DMI cycle on a
SCI on AUX 3 Thermal Sensor Trip (AUX3SCI)
0 = Disable reporting of this condition via SCI messaging.
1 = Does not mask the generation of an SCI DMI cycle on an
SCI on AUX 2 Thermal Sensor Trip (AUX2SCI)
0 = Disable reporting of this condition via SCI messaging.
1 = Does not mask the generation of an SCI DMI cycle on an
SCI on AUX 1 Thermal Sensor Trip (AUX1SCI)
0 = Disable reporting of this condition via SCI messaging.
1 = Does not mask the generation of an SCI DMI cycle on an
SCI on AUX 0 Thermal Sensor Trip (AUX0SCI)
0 = Disable reporting of this condition via SCI messaging.
1 = Does not mask the generation of an SCI DMI cycle on an
0/0/0/MCHBAR
10E6h
00h
RO; RW
8 bits
catastrophic thermal sensor trip.
Hot thermal sensor trip.
Aux3 thermal sensor trip.
Aux2 thermal sensor trip.
Aux1 thermal sensor trip.
Aux0 thermal sensor trip.
Description
129