CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 66

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.8.18
1.8.19
66
REMAPBASE - Remap Base Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
REMAPLIMIT - Remap Limit Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
15:10
15:10
9:0
Bit
9:0
Bit
Access
Access
RW-L
RW-L
RO
RO
000000b
Default
000000b
Value
Default
000h
Value
3FFh
Reserved
Remap Limit Address [35 26] (REMAPLMT)
The value in this register defines the upper boundary of the
Remap window. The Remap window is inclusive of this
address. In the decoder A[25:0] of the remap limit address
are assumed to be F. Thus the top of the defined range is one
byte less than a 64-MB boundary.
When the value in this register is less than the value
programmed into the Remap Base register, the Remap
window is disabled.
These Bits are Intel VT-d lockable or Intel ME stolen Memory
lockable.
Reserved
Remap Base Address [35 26] (REMAPBASE)
The value in this register defines the lower boundary of the
Remap window. The Remap window is inclusive of this
address. In the decoder A[25:0] of the Remap Base Address
are assumed to be 0's. Thus the bottom of the defined
memory range is aligned to a 64-MB boundary.
When the value in this register is greater than the value
programmed into the Remap Limit register, the Remap
window is disabled.
These bits are Intel VT-d lockable or Intel ME stolen Memory
lockable.
0/0/0/PCI
98-99h
03FFh
RO; RW-L
16 bits
0/0/0/PCI
9A-9Bh
0000h
RO; RW-L
16 bits
Description
Processor Configuration Registers
Description
Datasheet